1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of controlling the CMP process so that the oxide thickness over the top capacitor plate is well controlled in the fabrication of integrated circuits.
2. Description of the Prior Art
A dynamic random access memory (DRAM) device includes a number of memory cells in or on a semiconductor substrate. Each memory cell includes a capacitor for storing information and a transistor for selecting a particular capacitor. In the conventional DRAM process, the oxide film overlying the top plate electrode of a capacitor is planarized using chemical mechanical polishing (CMP). This process must have very tight thickness control in order to adequately protect the underlying capacitor. CMP has difficulty controlling thickness uniformity; the underlying capacitor plate may be damaged. This may cause a short during subsequent metal deposition and etching. The oxide film may be made thicker to prevent this occurrence. However, if the interlevel dielectric layer, of which the oxide is part, is too thick, this will lead to difficulties in contact etching. It is desired to achieve good oxide thickness control over the top plate electrode of a capacitor while not increasing the contact etch oxide thickness in a CMP process.
U.S. Pat. No. 5,714,779 to Auer et al shows two dielectric layers overlying a top plate electrode of a capacitor. The topmost layer is planarized by CMP. No mention is made of a CMP stop layer. U.S. Pat. No. 5,663,108 to Lin teaches planarizing a layer of oxide overlying a spinon-glass layer using CMP. U.S. Pat. Nos. 5,385,866 to Bartush and 5,324,690 to Gelatos et al disclose a boron nitride polish stop layer for CMP. U.S. Pat. Nos. 5,362,669 to Boyd et al and 5,262,348 to Bindal et al disclose silicon nitride stop layers in trench filling. U.S. Pat. No. 5,246,884 to Jaso et al teaches a diamond or diamond-like carbon stop layer for polishing the dielectric over metal lines. None of these references using polish stop layers address the planarization of a dielectric layer over capacitors.